GuillemLP

GuillemLP

PhD student at BSC

About me

I am a PhD student (3rd year) in Computer Architecture at Barcelona Supercomputing Center (BSC) and Polytechnic University of Catalonia (UPC). I focus on mechanisms to connect coherent hardware accelerators to the memory hierarchy of the CPU. Currently, I have collaborations with industry (Arm), and Academia (UCSB). I have 3 papers at international conferences as first author (ICPP 21, DATE 23, SAMOS 23), and several papers at journals and conferences as co-author (DCIS, DSD, DATE). I received a schoalrship to do the PhD from the catalan governement as well as funding from Arm to do reserach.

I am always looking for further collaborations or internships/research stages. My interests include networks, interconnects for accelerators, hardware accelerators, FPGA, RTL Simulation, Simulators, and in general Computer Architecture.

I am currently looking for new RTL projects to be accelerated by Metro-MPI. Metro-MPI is a methodology to speed-up RTL Simulations using MPI. It works particularly well in OpenPiton, obtaining super-linear speeupds with Verilator. You can find more info at: www.github.com/metro-mpi

Education

  • Ph.D in Computer Architecture, Polytechnic University of Catalonia (UPC), 2024 (expected)
    • Visiting PhD Student at University of California, Santa Barbara (UCSB), Oct 22 - March 23
    • International Collaborations with Arm and UCSB
    • 4 month research stage at Univeristy of California, Santa Barbara (UCSB) (Oct 22 - March 23)
  • M.S. in Innovation and Research in Informatics, Polytechnic University of Catalonia (UPC), 2020
    • Specialization in High Performance Computing (HPC)
  • B.S. in Informatics Engineering, Polytechnic University of Catalonia (UPC), 2017
    • BSc mobility exchange, Ecole Polytechnique Federale De Lausanne (EPFL) , 2017

Work experience

  • Summer 2021, Google Summer of Code Student with Fossi Foundation
    • Parallelized RTL simulations with MPI (using up to 1024 cores) with speedups of 134×
  • Summer 2018, Google Summer of Code Student with Performance Co‑Pilot (PCP)
    • Added a new functionality into production.
  • August 2017 - March 2018, Intern at Xilinx Labs (XLABS)
    • Studied the scalability of the new Accelerator (ACAP) and in charge of the nighly regression of the simulator.

Publications

  • Characterization of a coherent hardware accelerator framework for SoCs
    Guillem López-Paradís, Balaji Venu, Adrià Armejach, Miquel Moreto
    International Conference / Workshop on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), July 2023
  • Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi
    Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó, Jonathan Balkind
    Design, Automation, and Test in Europe (DATE), April 2023
  • SQuadS: Self-Serve System Services for new Hardware-Software Cooperation
    N. Turtayeva, G. López Paradís, J. Balkind
    Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), March 2023
  • DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
    G. Cabo, G. Candón, X. Carril, M. Doblas, M. Domínguez, A. González, C. Hernández, V. Jiménez, V. Kostalampros, R. Langarita, N. Leyva, Guillem López-Paradís, et al.
    37th Conference on Design of Circuits and Integrated Systems (DCIS), November 2022
  • Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI
    V. Soria Pardos, M. Doblas, Guillem López-Paradís, G. Candón, N. Rodas, X. Carril, P. Fontova-Musté, N. Leyva, S. Marco-Sola, M. Moretó
    25th Euromicro Conference on Digital System Design (DSD), September 2022
  • Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors
    A. Armejach, B. Brank, J. Cortina, F. Dolique, T. Hayes, N. Ho, Pierre-Axel Lagadec, R. Lemaire, Guillem López-Paradís, L. Marliac, M. Moretó, P. Marcuello, D. Pleiter, X. Tan, S. Derradji
  • gem5+rtl: A Framework to Enable RTL Models Inside a Full-System Simulator
    Guillem López-Paradís, Adrià Armejach, Miquel Moretó
    50th International Conference on Parallel Processing (ICPP), August 2021
  • An Academic RISC-V Silicon Implementation Based on Open-Source Components
    J. Abella, C. Bulla, G. Cabo, F. J. Cazorla, A. Cristal, M. Doblas, R. Figueras, A. González, C. Hernández, C. Hernández, V. Jiménez, L. Kosmidis, V. Kostalabros, R. Langarita, N. Leyva, Guillem López-Paradís, J. Marimon, R. Martínez, J. Mendoza, F. Moll, M. Moretó, J. Pavón, C. Ramírez, M. Antonio Ramírez, C. Rojas Morales, A. Rubio, A. Ruiz, N. Sönmez, V. Soria, L. Terés, O. S. Unsal, M. Valero, I. Vargas Valdivieso, L. Villa
    XXXV Conference on Design of Circuits and Integrated Systems (DCIS), November 2020

Achivements and awards

  • DAC Young Fellow, 2023
  • Mobility grant from BSC, 2022
  • PhD grant FI, 2021
  • GSoC Student 2021
  • Nacho Navarro grant, 2019
  • Participated in more than 15 hackathons (3rd prize in Hack the Burgh and Octocat Prize, finalist team in Copenhacks), 2018
  • GSoC Student 2018
  • Undergrad Research grant (Beca de Colaboración), 2017
  • Accepted at the most prestigious start‑up program led by Santander bank for undergrads
  • Involved in different associations during the Bachelor and Master at UPC, including HackUPC, 2015-2018
  • Grant for the best 16 years‑old students of the Valencian region in order to discover the research world at Polytechnic University of Valencia (UPV), 2012