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A list of all the posts and pages found on the site. For you robots out there is an XML version available for digesting as well.
Pages
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Posts
Future Blog Post
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Blog Post number 4
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Blog Post number 3
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Blog Post number 2
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Blog Post number 1
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portfolio
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publications
An Academic RISC-V Silicon Implementation Based on Open-Source Components
Published in DCIS 2020, 2020
First academic RISC-V silicon tape-out at BSC built entirely from open-source components — early predecessor of the DVINO and Sargantana SoCs.
Recommended citation: Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, et al. (2020). "An Academic RISC-V Silicon Implementation Based on Open-Source Components" DCIS 2020. https://doi.org/10.1109/DCIS51330.2020.9268664
Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors
Published in DATE 2021, 2021
Overview of the Mont-Blanc 2020 EU project, designing scalable and power-efficient European HPC processor IPs.
Recommended citation: Adrià Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem López-Paradís, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji. (2021). "Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors" DATE 2021. https://doi.org/10.23919/DATE51398.2021.9474093
gem5+rtl: A Framework to Enable RTL Models Inside a Full-System Simulator
Published in ICPP 21, 2021
This paper is about a flexible framework that enables simulation of RTL models inside a full-system software simulator.
Recommended citation: Guillem López-Paradís, Adrià Armejach, Miquel Moretó. (2021). "gem5+rtl: A Framework to Enable RTL Models Inside a Full-System Simulator" ICPP 2021. https://doi.org/10.1145/3472456.3472461
Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI
Published in DSD 2022, 2022
First DSD paper introducing Sargantana, a 1 GHz+ in-order RISC-V core with SIMD vector extensions in 22nm FD-SOI.
Recommended citation: Víctor Soria Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, Miquel Moretó. (2022). "Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI" DSD 2022. https://doi.org/10.1109/DSD57027.2022.00042
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
Published in DCIS 2022, 2022
Tape-out of DVINO, a RISC-V vector processor implemented in 65nm — predecessor SoC in the BSC academic tape-out line that culminated in Sargantana.
Recommended citation: Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, et al. (2022). "DVINO: A RISC-V Vector Processor Implemented in 65nm Technology" DCIS 2022. https://doi.org/10.1109/DCIS55711.2022.9970128
Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi
Published in DATE 23, 2023
This paper is about accelerating RTL Simulations with MPI.
Recommended citation: Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó, Jonathan Balkind. (2023). "Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-MPI" DATE 2023. https://doi.org/10.23919/DATE56975.2023.10137080
Characterization of a coherent hardware accelerator framework for SoCs
Published in SAMOS 23, 2023
This paper is about a Characterization of a framework for hardware accelerators from Arm, ACAI.
Recommended citation: Guillem López-Paradís, Balaji Venu, Adrià Armejach, Miquel Moretó. (2023). "Characterization of a Coherent Hardware Accelerator Framework for SoCs" SAMOS 2023, pp. 91–106. https://doi.org/10.1007/978-3-031-46077-7_7
OpenPiton Optimizations Towards High Performance Manycores
Published in NoCArc @ MICRO 2023, 2023
NoCArc workshop paper characterising and optimising the OpenPiton NoC and memory hierarchy to scale toward HPC-class manycores.
Recommended citation: Neiel Leyva, Alireza Monemi, Noelia Oliete-Escuín, Guillem López-Paradís, Xabier Abancens, Jonathan Balkind, Enrique Vallejo, Miquel Moretó, Lluc Alvarez. (2023). "OpenPiton Optimizations Towards High Performance Manycores" NoCArc @ MICRO 2023. https://doi.org/10.1145/3610396.3623265
Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology
Published in DCIS 2023, 2023
Tape-out of Sargantana, a 1 GHz+ academic in-order RISC-V SoC with vector extensions in 22nm FD-SOI, delivered through a multi-team collaboration at BSC.
Recommended citation: Max Doblas, Gerard Candón, Xavier Carril, Marc Domínguez, Enric Erra, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, et al. (2023). "Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology" DCIS 2023. https://doi.org/10.1109/DCIS58620.2023.10335976
GenArchBench: A Genomics Benchmark Suite for Arm HPC Processors
Published in Future Generation Computer Systems, 2024
A reproducible genomics benchmark suite targeting Arm-based HPC processors, providing characterised kernels for short- and long-read alignment, variant calling, and sequence search.
Recommended citation: Lorién López-Villellas, Rubén Langarita-Benítez, Asaf Badouh, Víctor Soria Pardos, Quim Aguado-Puig, Guillem López-Paradís, Max Doblas, Javier Setoain, Chulho Kim, Makoto Ono, Adrià Armejach, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó. (2024). "GenArchBench: A genomics benchmark suite for arm HPC processors" Future Generation Computer Systems, 157, 313–329. https://doi.org/10.1016/j.future.2024.03.050
The Case For Data Centre HyperLoops
Published in ISCA 2024, 2024
Co-first author ISCA’24 work on accelerator-coherent data movement fabrics achieving 114.8×–646.4× over a 400 Gbps optical network.
Recommended citation: Guillem López-Paradís (co-first), Isaac M. Hair, Sid Kannan, Roman Rabbat, Parker Murray, Alex Lopes, Rory Zahedi, Winston Zuo, Jonathan Balkind. (2024). "The Case For Data Centre HyperLoops" ISCA 2024. https://doi.org/10.1109/ISCA59077.2024.00026
OpenPiton4HPC: Optimizing OpenPiton Toward High-Performance Manycores
Published in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2024
Journal extension presenting micro-architectural and memory-system optimizations that push the OpenPiton open-source manycore toward HPC-class performance.
Recommended citation: Neiel Leyva, Alireza Monemi, Noelia Oliete-Escuín, Guillem López-Paradís, Xabier Abancens, Jonathan Balkind, Enrique Vallejo, Miquel Moretó, Lluc Alvarez. (2024). "OpenPiton4HPC: Optimizing OpenPiton Toward High-Performance Manycores" IEEE JETCAS, 14(3). https://doi.org/10.1109/JETCAS.2024.3428929
talks
Exascale Simulation of Next-Generation Computing Architectures
Published:
Invited workshop talk at IISWC 2023 on scaling RTL simulation toward exascale-class architectures using Metro-MPI and distributed simulation infrastructures.
Past, Present and Future of Designing, Integrating and Simulating RTL Models
Published:
Invited seminar at Politecnico di Milano covering the evolution of RTL design and simulation: from gem5+RTL to Metro-MPI, the move toward billion-transistor SoC simulation, and emerging directions in agent-driven hardware design.
teaching
Teaching experience 1
Undergraduate course, University 1, Department, 2014
This is a description of a teaching experience. You can use markdown like any other post.
Teaching experience 2
Workshop, University 1, Department, 2015
This is a description of a teaching experience. You can use markdown like any other post.