An Academic RISC-V Silicon Implementation Based on Open-Source Components
Published in DCIS 2020, 2020
Recommended citation: Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, et al. (2020). "An Academic RISC-V Silicon Implementation Based on Open-Source Components" DCIS 2020. https://doi.org/10.1109/DCIS51330.2020.9268664
First BSC academic RISC-V silicon tape-out built entirely from open-source components — early predecessor of the DVINO and Sargantana SoCs.
Recommended citation: Abella, J., Bulla, C., Cabo, G., Cazorla, F. J., Cristal, A., Doblas, M., Figueras, R., González, A., Hernández, C., Hernández, C., Jiménez, V., Kosmidis, L., Kostalabros, V., Langarita, R., Leyva, N., López-Paradís, G., et al. (2020). “An Academic RISC-V Silicon Implementation Based on Open-Source Components” DCIS 2020.