About me

I am a postdoctoral researcher and research lead at the Barcelona Supercomputing Center (BSC), specialising in RTL simulation scalability, coherent accelerator memory systems, and scalable MPMC queue‑based communication for accelerators. I completed my PhD in Computer Architecture (Cum Laude) at BSC–UPC in July 2025, with a thesis on Efficient Data Movement in Large‑Scale Heterogeneous Systems.

I currently lead a team of four researchers at BSC, coordinating international collaborations with UCSB and Politecnico di Milano. I am driving a new research direction on LLM-based, agent-driven workflows for hardware design — automated RTL generation, architectural exploration, and hardware–software co-design.

I serve on the program committees for ISCA ’26, MICRO ’26, CF ’26, and on the artifact evaluation committees for ISCA ’26 and ASPLOS ’26.

For my full background see my CV, the publications list, and the talks page.

Recent

• Apr 2026

  PC member, MICRO 2026

  Joined the program committee for the 59th IEEE/ACM International Symposium on Microarchitecture.

• 2025

  Invited seminar at Politecnico di Milano

  Past, Present and Future of Designing, Integrating and Simulating RTL Models.

• Under review

  Advanced Communications Patterns for HW Accelerators

  First-author paper extending Metro-MPI's MPMC queue model to a wider class of accelerator integration patterns.

Get in touch

The fastest way to reach me is by email. I am open to collaborations on accelerator coherence, RTL simulation scalability, Metro-MPI integrations, and LLM-driven hardware design — and to research / engineering roles in computer architecture and hyperscale systems. Profiles: Google Scholar · GitHub · LinkedIn · ORCID.