DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
Published in DCIS 2022, 2022
Recommended citation: Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, et al. (2022). "DVINO: A RISC-V Vector Processor Implemented in 65nm Technology" DCIS 2022. https://doi.org/10.1109/DCIS55711.2022.9970128
Tape-out of DVINO, a RISC-V vector processor in 65nm and a precursor SoC in the BSC academic tape-out line.
Recommended citation: Cabo, G., Candón, G., Carril, X., Doblas, M., Domínguez, M., González, A., Hernández, C., Jiménez, V., Kostalampros, V., Langarita, R., Leyva, N., López-Paradís, G., et al. (2022). “DVINO: A RISC-V Vector Processor Implemented in 65nm Technology” DCIS 2022.